1. Field of the Invention
The present disclosure relates to a semiconductor memory device and, more particularly, to a method of reading and writing data from/to the semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices are routinely tested for defects that may have occurred during the manufacturing process. During a typical memory test, a test engineer applies a command including an address and a data type to the memory device. Upon application of this command, an output is received from the memory device. If the output is in accordance with the input provided to the memory device, the memory device is considered to have passed the test.
With recent advances in semiconductor fabrication technology, semiconductor memory devices are becoming increasingly integrated in size, i.e., their size is being continually reduced. As part of this reduction in size, the line width of the semiconductor chip is being continually reduced. The line width of a chip is the distance between the edge of the wafer and the active are (i.e., memory cells) on the wafer. With a decrease in the line width of the semiconductor chip, the probability of manufacturing defects occurring on the chip increases. The increase in the probability of defects occurring in the chip has lead to increasing tests being performed to ensure the quality of the chip. As a consequence, testing times, and hence manufacturing costs, of semiconductor chips have increased.
Generally, I/O pins are used to write data to a memory device and also read data from the memory device. Because the same set of pins are used for reading and writing data from/to the memory device, a typical semiconductor memory device can not simultaneously perform the data read operation and the data write operation.
While a semiconductor memory device may have data input pads and data output pads, these data pads are configured to be commonly used for data input/output. Therefore, no simultaneous transmission and reception of data from the semiconductor memory device may occur via the data input pads and data output pads.
Because of the lack of simultaneous transmission and reception of data from memory devices, the test times for testing memory devices are generally high. This is because a tester has to first input all the test data and then, after inputting all the test data, receive data output from the memory device to determine whether the memory device has passed the test.
Various test modes have been developed in order to reduce the test time. For example, a conventional test method uses a parallel bit test (PBT) to simultaneously test a plurality of semiconductor memory devices. The PBT method does not receive and output data through all data I/O pads of the semiconductor memory device but does receive and output data through a predetermined number of representative data I/O pads, whereby a large number of semiconductor memory devices can be tested simultaneously.
However, even though a number of devices may be tested simultaneously, each test is still performed by first inputting test data and then, after all test data is input, receiving an output to determine whether the device under test as passed the test. That is, there is no method for simultaneously performing the data write operation and the data read operation.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device. The semiconductor memory device of FIG. 1 comprises a memory cell array 30, an address input buffer 10, a command decoder 12, a mode setting circuit 14, a clock buffer 16, a row address decoder 20, a column address decoder 22, a data write circuit 24, and a data read circuit 28. The memory cell array 30 comprises four memory banks BA_A, BA_B, BA_C, and BA_D. The functions of the components of FIG. 1 are described below.
The clock buffer 16 receives and buffers an external clock signal CLK to generate a buffered clock signal PCLK. The address input buffer 10 receives and buffers an external address ADD to generate an internal row address ra[14:0] in response to an active signal ACT and the buffered clock signal PCLK during an active operation. Furthermore, the address input buffer 10 also receives and buffers the external address ADD to generate an internal column address ca[14:0] in response to a write or read signal WE or RE respectively, and the buffered clock signal PCLK during the write or read operation.
The command decoder 12 receives a command signal CMD and decodes it in response to the buffered clock signal PCLK to generate the active signal ACT, the write signal WE and the read signal RE. The mode setting circuit 14 receives the command signal CMD and the external address ADD and decodes them in response to the buffered clock signal PCLK to generate a test mode setting signal TMRS.
The row address decoder 20 receives the internal row address ra[14:0] and the active signal ACT and decodes them under control of the test mode setting signal TMRS to activate one of a plurality of word selecting signals WL_A, WL_B, WL_C, and WL_D per each of the four memory banks BA_A, BA_B, BA_C, and BA_D. Similarly, the column address decoder 22 receives the buffered internal column address ca[14:0] and the active signal ACT and decodes them under control of the test mode setting signal TMRS to activate one of a plurality of column selecting signals CSL_A, CSL_B, CSL_C, and CSL_D per each of the four memory banks BA_A, BA_B, BA_C, and BA_D.
The data read circuit 28 receives parallel read data outputted from the memory cell array 30 to generate a predetermined number of serial output data Do under control of the test mode setting signal TMRS. Similarly, the data write circuit 24 receives write data Di which are serially input into the data write circuit 24 and converts them into parallel data under control of the test mode setting signal TMRS to generate input data to be input into the four memory banks BA_A, BA_B, BA_C, and BA_D.
The memory cell array 30 comprises the four memory banks BA_A, BA_B, BA_C, and BA_D, and receives write data from the data write circuit 24 in response to the data write signal WE and inputs the write data to each memory bank. In addition, the memory cell array 30 receives read data from each memory bank in response to the data read signal RE and outputs them to the data read circuit 28.
A row address RA and a column address CA are applied to the semiconductor memory device through address pins, and input and output data Di and Do applied to the memory cell array 30 are read from or written to the semiconductor memory device through common data request (DQ) pins or pads.
FIG. 2 is a timing diagram illustrating the data write and read operations of the conventional semiconductor memory device of FIG. 1. The external clock signal CLK, the command signal CMD, the input address signal ADD, the data I/O signal DQ, the test mode setting signal TMRS, the buffered clock signal PCLK, a plurality of memory bank word line selecting signals WL_A, WL_B, WL_C, and WL_D, and a plurality of memory bank column line selecting signals CSL_A, CSL_B, CSL_C, and CSL_D are shown in FIG. 2.
The external clock signal CLK is toggled with a predetermined phase and cycle. Furthermore, the buffered clock signal PCLK is toggled with the same cycle as the external clock signal CLK by buffering the external clock signal CLK.
The command signal CMD loads the active signal ACT, the data write commands WE of each memory bank, and the data read commands RE of each memory bank in order. In addition, the input address signal ADD loads the row address RA through the address pin according to the active command ACT, the column address CA for writing data according to the data write command WE, and the column address CA for reading data according to the data read command RE. Furthermore, in the data I/O signal DQ, write data Di_A-1 to Di_A-M of each of a plurality of memory banks are applied through data pins according to the data write signal WE and read data Do_A-1 to Do_A-M of each of a plurality of memory banks are outputted according to the data read signal RE.
FIG. 3 is an operation timing diagram illustrating data write and read operation time of a plurality of memory banks in the conventional semiconductor memory device of FIG. 1. In particular, the external clock signal CLK, the command signal CMD, and the data I/O signal DQ are shown in FIG. 3.
The buffered clock signal PCLK is toggled with a predetermined cycle, and data write commands WE_A, WE_B, WE_C, and WE_D and data read commands RE_A, RE_B, RE_C, and RE_D of the first to fourth memory banks are alternately loaded as the command signal CMD. In the data I/O signal DQ, a plurality of input data Di_A, Di_B, Di_C, and Di_D and a plurality of output data Do_A, Do_B, Do_C, and Do_D of the first to fourth memory banks are alternately loaded according to the data write commands WE_A, WE_B, WE_C, and WE_D and the data read commands RE_A, RE_B, RE_C, and RE_D of the first to fourth memory banks.
If a time spent to write/read data to/from one memory bank is defined as “T”, a time 8T is spent to perform both the data write and read operations in the first to fourth memory banks BA_A, BA_B, BA_C, and BA_D. In particular, the data write and read operations of the conventional semiconductor memory device during a testing operation are described below with reference to FIGS. 1 to 3.
The operation is described below based on the assumption that a plurality of word line selecting signals are n-bit signals, a plurality of column selecting signals are m-bit signals, and test write data Di and test read data Do are M serial data which are converted to (from) N-bit parallel data. First, an operation for sequentially writing data to the first to fourth memory banks BA_A, BA_B, BA_C, and BA_D in the memory cell array 30 from an external device to the semiconductor memory device is described below.
When the row address RA[14:0] of 15 bits is applied together with the active command ACT from the external portion, the command decoder 12 internally generates the active command ACT, and the address input buffer 10 buffers the row address RA to generate the buffered internal row address ra[14:0] of 15 bits in response to the buffered clock signal PCLK. At this time, the row address decoder 20 decodes 13 bits ra[12:0] of the internal row address ra[14:0] to generate word line selecting signals WL1 to WLn, so that one of the word line selecting signals WL1 to WLn is activated. At this time, the row address decoder 20 decodes 2 most significant bits ra[14:13] as the bank address to select the memory bank in the memory cell array 30. The 2 most significant bits may be “00”, “01”, “10” and “11” which represent the first to fourth memory banks BA_A, BA_B, BA_C, and BA_D.
Thereafter, when the column address CA[14:0] of 15 bits are applied together with the write command from the external portion, the command decoder 12 generates the write command WE, and the address input buffer 10 buffers the column address CA to generate the buffered column address ca[14:0] of 15 bits in response to the buffered clock signal PCLK. The column address decoder 22 decodes 13 bits ca[12:0] of the buffered internal column address ca[14:0] to generate a plurality of column selecting signals CSL1 to CSLm, so that one of the column selecting signals CSL1 to CSLm is activated. Like the row address decoder 20, the column address decoder 22 decodes 2 most significant bits ca[14:13] as the bank address to select the memory bank in the memory cell array 30.
The data write circuit 24 receives M write data Di_A-1 to Di_A-M which are serially inputted, converts them into N-bit parallel data under control of the test mode setting signal TMRS and writes them to memory cells of the selected memory bank of the memory cell array 30.
An operation for sequentially reading data from the first to fourth memory banks in the memory cell array 30 to the external portion is described below.
When the row address RA of 15 bits is applied from the external portion, the same operation as the active command ACT is applied in the above described data write operation is performed, so that one of the word line selecting signals WL1 to WLn and 2 most significant bits ca[14:13] are decoded as the bank address to select the memory bank of the memory cell array 30.
When the column address CA of 15 bits are applied together with the read command RE from the external portion, the command decoder 12 generates the read command RE, and the address input buffer 10 buffers the column address CA to generate the buffered internal column address ca[14:0] of 15 bits in response to the buffered clock signal PCLK.
The column address decoder 22 decodes 13 bits ca[12:0] of the buffered internal column address ca[14:0] to generate the column selecting signals CSL1 to CSLm, so that one of the column selecting signals CSL1 to CSLm is activated. Like the row address decoder 20, the column address decoder 22 decodes 2 most significant bits ca[14:13] as the bank address to select the memory bank in the memory cell array 30.
The data read circuit 28 receives M-bit parallel data outputted from the selected memory bank in the memory cell array 30, converts them into M serial data Di_A-1 to Di_A-M under control of the test mode setting signal TMRS and outputs them.
As described above, the conventional semiconductor memory device cannot perform the data write and read operations simultaneously because data applied through the data I/O pins from an external device are sequentially inputted to each of a plurality of memory banks and data is output sequentially to an external device through the same data I/O pins.
In a semiconductor chip testing scenario, the time taken to first input test data and then to receive outputted test results only after all the test data is input may increase the overall testing time. This problem may be exacerbated as the integration density of semiconductor memory devices increases. This is because as the integration density of semiconductor memory devices increases, the probability of manufacturing defects occurring on the devices also increases thus leading to increased testing times and hence, increased manufacturing costs.
Therefore, there is a need for a method for the simultaneous input of test data and output of the test results so as to reduce the test time for the semiconductor memory device. This reduction in the test time of the semiconductor memory device may lead to lower manufacturing costs, high system operation efficiency and a high speed system operation.